The greatly increased circuit density and speeds available within today's microchips has in turn resulted in correspondingly enhanced on-chip functional capability and performance. However, these enhancements have themselves begun to raise certain other concerns, such as the performance of conventional data bus techniques. The much higher off-chip input and output bandwidths (that is, data transfers to and from the microchip), which are necessary to make effective use of such greatly enhanced on-chip functional capability, are becoming much more difficult to provide.
One solution to this dilemma is to employ a wider bus data path. However, the increased numbers of bus data driver circuits required by this approach cause further problems for the chip designer. Depending on how different the data pattern being transferred in a given bus cycle is from that of the preceding bus cycle, anywhere between all and none of the data bus drivers may be required to change the voltage levels of their respective data bus lines. Since each data bus line may have a significant load capacitance, there could both be a significant peak total driver current requirement (if all drivers simultaneously and rapidly attempt to change the voltage levels of their bus lines), and significant variations in such driver current demand from one bus cycle to the next (if all switch in one cycle, for example, and none switch in the next). It becomes increasingly difficult to provide adequate power distribution to large numbers of such driver circuits, as the inductance and resistance of the on-chip power supply and ground grids feeding them results in significant dynamic bus data-dependent voltage shifts. These in turn are often coupled as noise to other circuitry on the chip.
One approach to this problem is to use driver circuits designed to limit slew rates, that is, how fast they change the voltage on their associated data bus line loads. Another is to “stagger” the driver circuit operation, so they do not all attempt to change their associated data bus lines at precisely the same instant. These methods are both effective, but at the cost of a longer bus cycle time, and slower data transfer rates.
Another approach is to use differential transmission, in which two wires are used for each data bus bit line. A constant current is then diverted down one driver circuit path or another to produce the differential signal. This typically results in lower ground and supply grid transients on-chip at the driver, with improved noise immunity at the receiver chip, since only the difference between the two data bus bit line voltage levels is significant to the differential receiver. This in turn allows lower voltage signal level swings to be used on the bus lines, which then reduces on-chip driver current demand for a given capacitive bus loading. Coupled noise within the data bus lines is also reduced, as is emitted electromagnetic radiation. This technique is generally referred to as LVDS (Low Voltage Differential Signal levels), to distinguish it from the single-ended type of bus where one wire is used to transmit each data bit, and the voltage levels used are typically the same as the logic circuitry.
Generally, the latter technique is used at this time for bus connections within a chip, and either the single-ended or LVDS methods for transmission between chips, depending on the speeds required, and the distance/load capacitance presented by the data bus lines.
U.S. Pat. No. 6,304,933 teaches a further improvement to the single-ended technique, which is called “Transitional Coding”. In this patent, data is transmitted through the activation or de-activation of one of four bus lines, each transition of one of the four bus lines representing a unique 2-bit binary value. The result is a reduced variation in driver current demand compared to a conventional single-ended approach, because two consecutive single-wire transitions are always required to transmit 4 bits of information, compared to anywhere from 0 to 4 simultaneous wire transitions over the same 4 wires if employed as part of a conventional single-ended data bus. In addition, the transitions are self-clocking, and can therefore be somewhat faster, especially in an on-chip environment.
Even using the LVDS technique, however, the numbers of driver circuits required for the increasingly wide bus data paths needed to supply adequate data transfer rates still present a significant on-chip simultaneous switching problem. The design of the bus system must allow for the possibility of each bus cycle transferring the inverse data pattern to that of the preceding one. All or none of the data lines might thus potentially be transitioned each cycle, and some of these might be differentially driven in the opposite sense to their adjacent neighbors, thereby increasing the effective inter-signal line load capacitance.
Variance in the number of switching bus lines resulting from such transitions frequently creates unfavorable conditions for receiving the encoded data, for such reasons as cross-coupling between lines, ground power voltage variations, noise spikes, electromagnetic radiation, and so on.
Therefore, there is a need for a method and an apparatus for differentially transmitting data on a bus that overcomes the limitations of conventional systems.